1. Field of the Invention
The present invention relates to an algorithm pattern generator for testing a memory device, and more particularly to an algorithm pattern generator for testing a memory device having a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in a memory tester for carrying out a test at a memory device module level or a component level.
2. Description of the Related Art
An algorithm pattern generator (hereinafter referred to as “ALPG”) is a device for generating a pattern in a memory tester used for testing a semiconductor device, especially a memory module or a memory component. The ALPG is used for coding an instruction in order to test data reading/writing operations.
A semiconductor tester, particularly a memory tester is designed and developed depending on development status of a memory device, especially that of a DRAM which takes a significant portion of the memory device. The development status of DRAM has evolved from a DRAM having an EDO (Extended Data Output) function, through SDRAM (Synchronous DRAM) and Rambus DRAM to DDR (Double Data Rate) DRAM.
In order to test these DRAMs, high speed and high accuracy are required for the memory testers. Moreover, as the capacity of the DRAM is increased, time necessary for the test is increased. Therefore, a test speed must be increased. A small and economical memory tester must be embodied in order to reduce the test cost.
FIG. 1 is a block diagram exemplifying a conventional tester.
Referring to FIG. 1, a memory tester 100 comprises a power supply 110 for supplying power voltage to a memory device 180 to be tested including a memory module or a memory component, a driver 120 for inputting a signal to an input unit of the memory device 180, a comparator 130 for comparing a signal output from an output unit of the memory device 180 with an expected value, a pattern generator 140 for generating a signal array (test pattern) which is input to the memory device 180 and an expected value signal, a timing generator 150 for generating timing for a signal which is input to the memory device 180, a CPU 160 which is a controller for controlling these circuits. The CPU 160 is configured to read from an external storage device and interpret the read data by an operating system (OS), thereby performing a generation and a determination of a signal for the test (test pattern) and carrying out predetermined tests. The tester 100 may comprise a DC test circuit 170 for carrying out a DC test such as detection of a voltage level of the output unit.
Since the above-described conventional memory tester performs a DC test for testing whether DC parameters are suitable for digital circuit operations and an AC margin test related to signal transmission delay time, set-up time and hold time, and comprises various components such as the timing generator, an expensive dedicated equipment having a large size such as a main frame is required to manufacture the conventional memory tester. Therefore, the conventional memory tester is disadvantageous in that the manufacturing cost is very high. It is preferable for memory manufacturers to minimize the production cost and to design an efficient memory tester so as to remain competitive in the market. Therefore, the memory tester must be efficiently designed to maintain a small size and reduce the production cost.
In order to achieve miniaturization of the tester, a technology for optimizing ALPG which is related to a generation of test patterns have been proposed.
For example, such an ALPG is disclosed in Korean Patent Application No. 2001-0045014 file by Hitachi Ltd. On Jul. 26, 2001, titled “A METHOD FOR GENERATING TESTER CONSTRUCTION DATA, CONSTRUCTION METHOD FOR TESTER AND TEST CIRCUIT”.
FIG. 2 is a block diagram illustrating an algorithm pattern generator disclosed by the Korean Patent Application No. 2001-0045014.
Referring to FIG. 2, the conventional ALPG comprises an instruction memory 210 for storing a micro program consisting of a plurality of micro instructions configured according to a test pattern generating algorithm, a program counter 220 for designating which is to be read from the instruction memory 210, a sequence control circuit 230 for generating a control signal for a memory circuit by decoding a instruction code in the micro instruction read out from the instruction memory 210 or a function block that constitutes ALPG such as the program counter 220, an address operation circuit 240 for generating a test address according to the micro instruction read out from the instruction memory 210, and a test data generating circuit 250 for generating a test data and a expected value data according to the read micro instruction.
Moreover, when determining whether the memory circuit under test is normal or not, means for determining whether the data read out from the memory circuit is consistent with the written data by comparing the same may be included. In addition, as shown in FIG. 2, the micro instruction stored in the instruction memory 210 includes an address field MPa for storing a PC (Program Counter) address denoting a jump address of a instruction used as a jump instruction, an OPcode field MFb for storing a sequence control code, an operand field MFc for storing the number of repeated instruction, a control field MFd for storing a control code for commanding an output and read/write operation of an address or a data, an address operation code field MFe for storing an address operation instruction code, and a data generation code field MFf for storing data generation instruction code.
However, the Korean Patent Application No. 2001-0045014 does not disclose an address scrambling or a data scrambling at all. The address scrambling refers to a mutual conversion for matching a physical address and a logical address (represented as row and column) of the memory. The data scrambling is represented as a function of an address. Since methods for minimizing an area of a layout differs depending on memory manufacturers, the scrambling of data is a process for conformity. In order to efficiently design the ALPG and optimize the configuration of the memory tester, the design of ALPG must take the scrambling into consideration.